Messages in this thread | | | Date | Fri, 27 Oct 2006 23:49:24 -0700 | From | thockin@hockin ... | Subject | Re: AMD X2 unsynced TSC fix? |
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On Fri, Oct 27, 2006 at 11:46:15PM -0700, Andrew Morton wrote: > On Fri, 27 Oct 2006 23:35:24 -0700 > thockin@hockin.org wrote: > > > On Fri, Oct 27, 2006 at 09:06:12PM -0700, Andi Kleen wrote: > > > > > > > So far, has I can understand. Seems to me that my computer which have a > > > > Pentium D (Dual Core) on VIA chipset, also have unsynchronized TSC and > > > > with the patch of hrtimers on > > > > > > Intel systems (except for some large highend systems) have synchronized TSCs. > > > > Does Intel guarantee that, or is that just what we happen to see, so far. > > Matthias has a Xeon machine on which the TSCs are unsynced, and which are > unsyncable - write_tsc() just doesn't do anything. See thread at > http://lkml.org/lkml/2006/7/22/104
Nothing at all, or just the the low few bits are writeable? I had heard, but never seen that some Intel CPUs only allowed 16 bits of writable bits in the TSC MSR. I also heard of, but never saw, CPUs that cleared the TSC to 0 on a write! - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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