Messages in this thread | | | Date | Fri, 27 Jan 2006 21:51:47 +0900 (JST) | Subject | Re: [PATCH 3/6] C-language equivalents of include/asm-*/bitops.h | From | Hirokazu Takata <> |
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Hello Mita-san, and folks,
From: mita@miraclelinux.com (Akinobu Mita) Subject: [PATCH 3/6] C-language equivalents of include/asm-*/bitops.h Date: Wed, 25 Jan 2006 20:32:06 +0900 > o generic {,test_and_}{set,clear,change}_bit() (atomic bitops) > > This patch introduces the C-language equivalents of the functions below: > void set_bit(int nr, volatile unsigned long *addr); > void clear_bit(int nr, volatile unsigned long *addr); ... > int test_and_change_bit(int nr, volatile unsigned long *addr); > > HAVE_ARCH_ATOMIC_BITOPS is defined when the architecture has its own > version of these functions. > > This code largely copied from: > include/asm-powerpc/bitops.h > include/asm-parisc/bitops.h > include/asm-parisc/atomic.h
Could you tell me more about the new generic {set,clear,test}_bit() routines?
Why do you copied these routines from parisc and employed them as generic ones? I'm not sure whether these generic {set,clear,test}_bit() routines are really generic or not.
> +/* Can't use raw_spin_lock_irq because of #include problems, so > + * this is the substitute */ > +#define _atomic_spin_lock_irqsave(l,f) do { \ > + raw_spinlock_t *s = ATOMIC_HASH(l); \ > + local_irq_save(f); \ > + __raw_spin_lock(s); \ > +} while(0) > + > +#define _atomic_spin_unlock_irqrestore(l,f) do { \ > + raw_spinlock_t *s = ATOMIC_HASH(l); \ > + __raw_spin_unlock(s); \ > + local_irq_restore(f); \ > +} while(0)
Is there a possibility that these routines affect for archs with no HAVE_ARCH_ATOMIC_BITOPS for SMP ? I think __raw_spin_lock() is sufficient and local_irqsave() is not necessary in general atomic routines.
If the parisc's LDCW instruction required disabling interrupts, it would be parisc specific and not generic case, I think, although I'm not familier with the parisc architecture...
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