Messages in this thread | | | Date | Fri, 13 Jan 2006 14:43:01 -0800 (PST) | Subject | Re: [PATCHSET] block: fix PIO cache coherency bug | From | "David S. Miller" <> |
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From: James Bottomley <James.Bottomley@SteelEye.com> Date: Fri, 13 Jan 2006 16:38:49 -0600
> Could someone explain (or give a reference to) the actual problem? If > it's a cache coherency issue it should show up with VIPT arhictectures > as well as VIVT ones ... I have access to parisc systems (with SCSI), > which are VIPT.
Not true, VIPT caches participate in cache coherency transactions with the PCI host controller (and thus the PCI device), whereas VIVT caches do not.
It does make a big difference, it's very hard to share datastructures with a device concurrently accessing them (what we call PCI consistent DMA mappings) on a VIVT cache. - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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