[lkml]   [2005]   [Sep]   [2]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
    SubjectRe: [PATCH 2.6.13] lockless pagecache 2/7
    From: Andi Kleen <>
    Date: 02 Sep 2005 22:41:31 +0200

    > > Yeah quite a few. I suspect most MIPS also would have a problem in this
    > > area.
    > cmpxchg can be done with LL/SC can't it? Any MIPS should have that.


    On PARISC, I don't see where they are emulating compare and swap
    as indicated. They are doing the funny hashed spinlocks for the
    atomic_t operations and bitops, but that is entirely different.

    cmpxchg() has to operate in an environment where, unlike the atomic_t
    and bitops, you cannot control the accessors to the object at all.

    The DRM is the only place in the kernel that requires cmpxchg()
    and you can thus make a list of what platform can provide cmpxchg()
    by which ones support DRM and thus provide the cmpxchg() macro already
    in asm/system.h

    We really can't require support for this primitive kernel wide, it's
    simply not possible on a couple chips.
    To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
    the body of a message to
    More majordomo info at
    Please read the FAQ at

     \ /
      Last update: 2005-09-02 23:15    [W:0.018 / U:6.324 seconds]
    ©2003-2016 Jasper Spaans. hosted at Digital OceanAdvertise on this site