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SubjectRe: [PATCH] i386: Selectable Frequency of the Timer Interrupt
On Fri, 15 Jul 2005, Venkatesh Pallipadi wrote:

> Well.. I tried a patch to do the broadcast thing couple of months ago and
> failed to convince everyone :(.

I must have missed the patch -- but was the change unconditional or
affecting only broken systems? And how such systems were determined?

> Further, it doesn't work well if you want to exclude some CPUs from the
> list of recievers. Logical destination is simple only for less than 8
> CPUs. Beyond that with clustered or physical configuration it is
> difficult.

Well, I've thought the number of bits for LDR has been reexpanded at one
point (it had been 32 originally with the 82489DX and then shrank to 8
with the Pentium integrated APIC) -- it must have been something else...

Anyway, for this you should just need a single bit as, quoting APIC
documentation:

"When the message addresses the destination using logical addressing
scheme each Local Unit in the ICC bus compares the logical address in the
interrupt message with its own Logical Destination Register. If there is
a bit match (i.e., if at least one of the corresponding pair of bits
match) this local unit is selected for delivery."

Thus you could make, say, bit 31 of LDR the "timer bit", set it in all
local APIC units and send timer interrupts in the Fixed delivery mode
using a logical destination address with only bit 31 set. You could then
exclude processors from delivery by clearing bit 31 of LDR as needed. It
could probably be applied to addresses within clusters, too, though space
there is a bit tight.

None of such hassle should be needed in reality, though -- I presume the
only broken systems are uniprocessor ones with the HT feature as real SMP
systems need to have their APICs enabled all the time to be able to accept
IPIs if nothing else. As UP systems with HT have only two processors
logically, there is no problem with using the logical destination mode as
currently implemented.

Maciej
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