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    SubjectRe: tricky challenge for getting round level-driven interrupt problem: help!
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    On Mer, 2005-05-04 at 21:58, Luke Kenneth Casson Leighton wrote:
    > i believe i get it: you raise a level-triggered interrupt which _stays_
    > raised until such time as your fifo is empty.

    Bingo. It only goes away when the chip really has nothing left to say.

    > all - that sometimes (frequently, in fact - about 1 in every
    > 50 times) it hasn't got round to clearing the level-driven
    > interrupt by the time we come out of the ARM ISR (!)

    So you'll poll again and find there is no pending work to do.

    > hence the redesign to do alternate read-write-read-write, and making
    > reads exclusive of writes, etc.

    and maybe even turn the IRQ off and use a timer if its slow and not
    sensitive to latency.. ?

    > ... so - in your opinion, alan, is the old approach we had
    > actually _on_ the right lines?

    level triggered IRQ does sort of expect the other end responds promptly
    to be efficient as opposed to merely reliable.

    > also, are you going to ukuug in august, it being _in_
    > aberystwyth and all :)

    Its not in Aberystwyth, but I might be. Its in Swansea 8)


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