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    SubjectRe: [rfc/patch] libata -- port configurable delays
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    On Gwe, 2005-05-13 at 21:03, Benjamin LaHaise wrote:
    > > 3) IIRC some rare PATA devices don't like having their Status register
    > > banged "too hard". No data, just a vague memory.

    Not that I am aware of. There are a few ICH/PIIX variants where if you
    read status during a transaction at the wrong time bad stuff occurs
    including to the block on disk. That may be what you are thinking of

    > >
    > > 4) It may be worthwhile to rewrite the loop to check the Status register
    > > _first_, then delay.

    The 400nS delay after a command is required before status becomes valid.
    This isn't about 'incorrect' devices in the command case. It is about
    strictly correct behaviour and propogation/response times. For the cases
    its not required and you wan to keep PCI load down then checking first
    is clearly logical.

    Also btw beware of PCI posting - writel/ndelay(400) isn't going to do
    the right thing.

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