Messages in this thread | | | Date | Sun, 3 Apr 2005 04:10:00 +0100 | From | Matthew Wilcox <> | Subject | Re: iomapping a big endian area |
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On Sat, Apr 02, 2005 at 06:38:05PM -0800, David S. Miller wrote: > > My thought on this is that we should encode the endianness of the > > registers in the ioremap cookie. Some architectures (sparc, I think?) can > > do this in their PTEs. The rest of us can do it in our ioread/writeN > > methods. I've planned for this in the parisc iomap implementation but > > not actually implemented it. > > SPARC64 can do it in the PTEs, but we just use raw physical > addresses in our I/O accessors, and in those load/store instructions > we can specify the endianness.
Ah right. So you'd prefer an ioread8be() interface?
> Be careful though. Endianness can be dealt with on a hardware > level. Consider a byte access to a 32-bit word sized config space > datum, the PCI controller on a big-endian system will likely byte-twist > the data lanes in order for this to work properly.
Yup, PA-RISC PCI adapters (both Dino and Elroy) do the same thing. The 53c700 driver handles this lack of skewing by xoring the address with 3.
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