lkml.org 
[lkml]   [2005]   [Dec]   [9]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [discuss] [patch] x86_64: align and pad x86_64 GDT on page boundary
On Fri, Dec 09, 2005 at 03:01:27PM -0800, Rohit Seth wrote:
> > > For the BP case it's ok as
> > > long as the beginning is correctly aligned and the rest
> > > is read-only.
> >
> > Just that any writes on the bp GDT will invalidate the idt_table cacheline,
> > which is read mostly (as Nippun pointed out). So could we keep the padding
> > as it is for the BP too?
> >
>
> Do you write into GDT often for this to be an issue. The reason I'm

The context switch writes into the GDT to switch around the TLS segments
when they are <4GB. Or in pre NPTL the same would be done for the LDT
also used for TLS.

> asking this because the per-cpu IDTs that Andi refered in the future.
> If we are really not using too many bytes in GDT then rest of the page
> can be used for IDT and such mostly RO data.

Once I implement that it can be shared with that page.

-Andi

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/

\
 
 \ /
  Last update: 2005-12-10 00:01    [W:0.092 / U:0.036 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site