[lkml]   [2005]   [Dec]   [17]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: [PATCH] UHCI: add missing memory barriers

> Looking at the PCI code, I see that the accesses are protected by a
> spinlock. Does that guarantee in-order execution of writes to
> configuration space with respect to writes to regular memory? On all
> platforms? If yes, then this barrier is not needed.

Hrm... there is a wmb in the unlock path, I suppose on all platforms,
and iirc, ppc & ppc64 implementation of config space accesses do a full
sync. On x86, they are IO ports, thus I would expect them to be fully
sychronous, but I can't guarantee that semantic is respected accross all

To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to
More majordomo info at
Please read the FAQ at

 \ /
  Last update: 2005-12-17 07:03    [W:0.029 / U:6.240 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site