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SubjectRe: [PATCH] UHCI: add missing memory barriers
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> Looking at the PCI code, I see that the accesses are protected by a
> spinlock. Does that guarantee in-order execution of writes to
> configuration space with respect to writes to regular memory? On all
> platforms? If yes, then this barrier is not needed.

Hrm... there is a wmb in the unlock path, I suppose on all platforms,
and iirc, ppc & ppc64 implementation of config space accesses do a full
sync. On x86, they are IO ports, thus I would expect them to be fully
sychronous, but I can't guarantee that semantic is respected accross all
architectures.


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