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SubjectRe: [PATCH 1/19] MUTEX: Introduce simple mutex implementation

On Fri, 16 Dec 2005, David S. Miller wrote:
> If there is some test guarding the CAS, yes.
> But if there isn't, for things like atomic increment and
> decrement, where the CAS is unconditional, you'll always
> eat the two bus transactions without the prefetch for write.

Side note: there may be hardware cache protocol _scheduling_ reasons why
some particular hw platform might prefer to go through the "Shared" state
in their cache protocol.

For example, you might have hardware that otherwise ends up being very
unfair, where the two-stage lock aquire might actually allow another node
to come in at all. Fairness and balance often comes at a cost, both in hw
and in sw.

Arguably such hardware sounds pretty broken, but the point is that these
things can certainly depend on the platform around the CPU as well as on
what the CPU itself does.

I'm not saying that that is necessarily what Jesse was arguing about, but
lock contention behaviour can be "interesting".

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