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SubjectRe: latest mtd changes broke collie

> >[Plus I get a warning from jffs2 that flashsize is not aligned to
> >erasesize. Then I get lot of messages that empty flash at XXX ends at
> >XXX.]
> The datasheet ref'ed earlier says the chips have a 64KB erase block
> size, and the sharp driver multiplies that value by an interleave of 4
> chips to set the erase size. What erase size is set under the new

I'm currently using:

.mfr_id = 0x00b0,
.dev_id = 0x00b0,
.name = "Collie hack",
.uaddr = {
.DevSize = SIZE_4MiB,
.NumEraseRegions= 1,
.regions = {
}, I should use ERASEINFO(0x40000,16)?

> setup? cat /proc/mtd or set loglevel for KERN_DEBUG at chip probe time.
> The new code is setting it based on what was read from the CFI query
> info reported by the chip times the interleave factor (which apparently
> should be set as 4 after detecting 4 chips if CONFIG_MTD_CFI_I4=y).

I do not have collie with me right now.
Thanks, Sharp!
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