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SubjectRe: what's next for the linux kernel?
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On Mon, 03 Oct 2005 22:07:22 BST, Luke Kenneth Casson Leighton said:

> whereas, would you see it more reasonable for a commodity-level
> chip to be something like 32- or even 64- ultra-RISC cores of
> between 5000 and 10,000 gates each, resulting in a processor
> of about 50% cache memory and 50% processing plus associated
> parallel bus architecture at around 1 million gates?

Read your history - especially IBM's 801 chipset, which became the RT,
and why they then replaced that with the Power architecture...

> running at oh say 1ghz or with careful design effort focussed on the
> RISC cores maybe even 2ghz, resulting in 128 total GigaOps if you
> go for 64 cpus @ 2ghz. that's a friggin lot of processing power
> for a 1m gates processor!!

Good. Were you planning to run the ucLinux branch on this, or include all
the pieces needed to support virtual memory? And do it inside that 10K gate
budget, too (hint - how many gates will you burn just doing a TLB big enough
to get the performance of mapping a virtual->real address to be good enough?)

You might want to read up on all the fun that IBM went through in designing
memory subsystems that can keep even the Power4 and Power5 chipsets fed too,
or the interesting stuff that SGI has to do to allow 64/128/512 processors
to beat up on a memory system - I'm sure there's some pretty high gate count
involved there..

If you're doing 64 10K-gate cores, you've blown 64% of your 1M gate budget.
You've got only 320K gates left to build cache *and* virtual memory support to
make that 1M gate budget. And yes, you need a cache, as IBM found out on
their RT processor.....

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