Messages in this thread | | | From | Herbert Xu <> | Subject | Re: Possible memory ordering bug in page reclaim? | Date | Sat, 15 Oct 2005 22:08:08 +1000 |
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Nick Piggin <nickpiggin@yahoo.com.au> wrote: > > Well yes, that's on the store side (1, above). However can't a CPU > still speculatively (eg. guess the branch) load the page->flags > cacheline which might be satisfied from memory before the page->count > cacheline loads? Ie. you can still have the correct write ordering > but have incorrect read ordering? > > Because neither PageDirty nor page_count is a barrier, and there is > no read barrier between them.
Yes you're right. A read barrier is required here.
I think Ben was actually agreeing with you. He's just questioning whether the corresponding write barrier existed on CPU 1 (the answer to which is affirmative).
Cheers, -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} <herbert@gondor.apana.org.au> Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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