Messages in this thread | | | Date | Mon, 31 Jan 2005 16:15:04 -0800 | From | Greg KH <> | Subject | Re: [PATCH 1/1] pci: Add Citrine quirk |
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On Fri, Jan 28, 2005 at 08:53:47AM -0600, brking@us.ibm.com wrote: > > The IBM Citrine chipset has a feature that if PCI config register > 0xA0 is read while DMAs are being performed to it, there is the possiblity > that the parity will be wrong on the PCI bus, causing a parity error and > a master abort. On this chipset, this register is simply a debug register > for the chip developers and the registers after it are not defined. > Patch sets cfg_size to 0xA0 to prevent this problem from being seen. > > Signed-off-by: Brian King <brking@us.ibm.com>
Applied, thanks.
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