Messages in this thread | | | Subject | Re: multi-domain PCI and sysfs | From | Alan Cox <> | Date | Wed, 08 Sep 2004 23:41:05 +0100 |
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On Mer, 2004-09-08 at 19:21, David S. Miller wrote: > On ppc, sparc, and other non-x86 platforms, when you perform load/store > instructions within the port I/O space window, the PCI controller emits > the IN/OUT transactions exactly as if an x86 processor had executed > an in{bwl}/out{bwl} instruction.
Some of them are not quite that pretty. In certain cases outb gets translated into code that does horrors vaguely of the form
spin_lock_irqsave lane = (addr & 3) << 3; writel(1<<(addr&3), somecontroller->lanes); writel(addr, somecontroller->offset); writel(val << lane, somecontroller->somewhere); spin_unlock_irqrestore
Other code has extra magic reads in to work around fpga pci bridges that forgot out is synchronous and writel is posted.
A better summary from the higher levels of the kernel would be "don't look behind the sofa, there might be a monster lurking".
The only way I can see VGA routing working is to have some kind of arch code that can tell you which devices are on the same VGA legacy tree. That then allows a vga layer to walk VGA devices and ask arch code the typically simple question
pci_vga_shared_router(pdev1, pdev2)
Alan
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