Messages in this thread | | | Subject | Re: bug in md write barrier support? | From | Alan Cox <> | Date | Wed, 08 Sep 2004 23:21:39 +0100 |
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On Mer, 2004-09-08 at 16:46, Jens Axboe wrote: > That's a worry if it really does that - does it, or are you just > speculating about possible problems?
I2O defines cache flush very losely. It flushes the cache and returns when the cache has been flushed. From playing with the controllers I have it seems some at least merge further queued writes into the output stream. Thus if I issue
write 1, 2, 3, 4 , 40, 41, flush cache, write 5, 6, 100
it'll write 1,2,3,4,5,6, 40, 41, report flush cache complete.
Obviously I can implement full barrier semantics in the driver if need be but that would cost performance hence the question.
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