Messages in this thread | | | Date | Tue, 10 Aug 2004 00:12:16 +0400 | From | Vladislav Bolkhovitin <> | Subject | Re: [PATCH] x86 bitops.h commentary on instruction reordering |
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Marcelo Tosatti wrote: > Vladislav, > > There is no cache coherency issues on x86, it handles the cache coherency > on hardware.
Well, Marcelo, sorry if I'm getting too annoying, but we had a race with cache coherency during SCST (SCSI target mid-level) development. We discovered that on P4 Xeon after atomic_set() there is very small window, when atomic_read() on another CPUs returns the old value. We had to rewrite the code without using atomic_set(). Isn't it cache coherency issue?
And, BTW, returning to the original topic, would it be better to make set_bit() and friends guarantee not to be reordered on all architectures, instead of just add the comment. Otherwise, what is the difference with versions with `__` prefix (__set_bit(), for example)? Just adding the comments will lead to creating different functions with gurantees by everyone who need it in all over the kernel. Is it the right thing? In some places in SCST we heavy rely on non-ordering guarantees.
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