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Subjectix86 Atomic ops during DMA...


A piece of hardware needs its interrupt status written back
to its status register to "clear" interrupts and thus enable
more.. This is in an uninterruptible ISR. This, of course
can be readily accomplished by using the standard readl() and
writel() macros.........but! If a DMA is in progress, a hardware
debugger shows many milliseconds between the read and the write.

This allows a race condition to exist. So, how do I lock the bus
during the read and write? A lock on ix86 locks only the
next instruction, not the next plus time for another lock
which appears to be needed.

I need...

movl (%ebx), %eax # Read status from register in ebx
movl %eax, (%ebx) # Write it back occur together without the bus being taken away by a DMA
operation until these two instructions are complete.

Dick Johnson
Penguin : Linux version 2.4.26 on an i686 machine (5570.56 BogoMips).
Note 96.31% of all statistics are fiction.

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