Messages in this thread | | | Subject | Re: [patch] voluntary-preempt-2.6.9-rc1-bk4-Q5 | From | Lee Revell <> | Date | Tue, 31 Aug 2004 16:10:34 -0400 |
| |
On Tue, 2004-08-31 at 16:09, Ingo Molnar wrote: > * Ingo Molnar <mingo@elte.hu> wrote: > > > it's more complex than that - MTRR's are caching attributes that the > > CPU listens to. Mis-setting them can cause anything from memory > > corruption to hard lockups. The question is, does any of the Intel (or > > AMD) docs say that the CPU cache has to be write-back flushed when > > setting MTRRs, or were those calls only done out of paranoia? > > the Intel docs suggest a cache-flush when changing MTRR's, so i guess > we've got to live with this. _Perhaps_ we could move the cache-disabling > and the wbinvd() out of the spinlocked section, but this would make it > preemptable, possibly causing other tasks to run with the CPU cache > disabled! I'd say that is worse than a single 0.5 msec latency during > MTRR setting. >
File under boot-time stuff, I guess. This could be bad if X crashes, but I can't remember the last time this happened to me, and I use xorg CVS.
Lee
- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
| |