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    Subject[PATCH][PPC32] Fix dual UICs in 4xx PIC support
    Fixes a case where we were not correctly acking the base cascade
    controller on PPC4xx. Patch from Pavel Bartusek <pba@sysgo.com>

    Signed-off-by: Matt Porter <mporter@kernel.crashing.org>

    ===== arch/ppc/syslib/ppc4xx_pic.c 1.10 vs edited =====
    --- 1.10/arch/ppc/syslib/ppc4xx_pic.c Tue May 18 07:48:10 2004
    +++ edited/arch/ppc/syslib/ppc4xx_pic.c Wed Jun 30 18:21:16 2004
    @@ -234,6 +234,9 @@
    case 1:
    mtdcr(DCRN_UIC_ER(UIC1), ppc_cached_irq_mask[word]);
    mtdcr(DCRN_UIC_SR(UIC1), (1 << (31 - bit)));
    +#if (NR_UICS == 2)
    + mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - UIC0_UIC1NC)));
    +#endif
    #if (NR_UICS > 2)
    mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
    #endif
    @@ -285,6 +288,9 @@
    break;
    case 1:
    mtdcr(DCRN_UIC_SR(UIC1), 1 << (31 - bit));
    +#if (NR_UICS == 2)
    + mtdcr(DCRN_UIC_SR(UIC0), (1 << (31 - UIC0_UIC1NC)));
    +#endif
    #if (NR_UICS > 2)
    mtdcr(DCRN_UIC_SR(UICB), UICB_UIC1NC);
    #endif
    @@ -423,7 +429,7 @@
    bit, sense);
    #endif
    ppc_cached_sense_mask[word] |=
    - (sense & IRQ_SENSE_MASK) << (31 - bit);
    + (~sense & IRQ_SENSE_MASK) << (31 - bit);
    ppc_cached_pol_mask[word] |=
    ((sense & IRQ_POLARITY_MASK) >> 1) << (31 - bit);
    switch (word) {
    -
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