Messages in this thread | | | Subject | Re: PAT support | From | (Eric W. Biederman) | Date | 15 Apr 2004 12:39:00 -0600 |
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Andi Kleen <ak@muc.de> writes:
> > This would also be extremely useful on machines with large amounts > > of memory, for write-back mappings. With large amounts but odd sized > > entries it becomes extremely tricky to map all of the memory using > > mtrrs. > > Yes agreed. I already had vendors complaining about this. > But for this it will need some more work - the MTRRs need to be fully > converted to PAT and then disabled (because MTRRs have > higher priority than PAT). Doing so is a lot more risky than > what Terrence's patch does currently though. But longer term > we will need it.
Ugh. You are right. The processors look at the two types and pick the one that caches the least. So PAT can't enable caching :(
> Also it will still need to handle overlapping ranges. I suppose > it will need some simple rules like: converting from UC to WC is > always ok.
Right.
That plus it should have some additional rules like the e820 map trumps the mtrrs in specifying what is memory so should be cacheable.
Eric
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