Messages in this thread Patch in this message | | | Date | Thu, 4 Nov 2004 13:22:38 -0800 | From | Tony Lindgren <> | Subject | Re: [PATCH] Serial updates |
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* Russell King <rmk+lkml@arm.linux.org.uk> [041102 15:27]: > > Ok, I'll send a pull request imminently. For those who don't want to > wait, latest patch against Linus' tree is at: > > http://www.arm.linux.org.uk/~rmk/misc/linus-serial.diff
I tried the current BK tree on omap, and the serial ports work with the following patch.
However, on omap 1510, the change of interrupt return value in serial8250_interrupt from IRQ_HANDLED to IRQ_RETVAL(handled) causes a problem on the first RX interrupt. It looks like the IIR register is not ready for reading right away, and at first shows that no interrupt happened (UART_IIR_NO_INT stays high).
This is probably a hardware issue, but might trigger something similar on other hardware as well.
Regards,
Tony --- linus/drivers/serial/8250.c 2004-11-03 09:50:58.000000000 -0800 +++ linux-omap-dev/drivers/serial/8250.c 2004-11-04 13:14:22.000000000 -0800 @@ -1692,6 +1693,17 @@ serial_outp(up, UART_EFR, efr); } +#ifdef CONFIG_ARCH_OMAP1510 + /* Workaround to enable 115200 baud on OMAP1510 internal ports */ + if (cpu_is_omap1510() && is_omap_port(up->port.membase)) { + if (baud == 115200) { + quot = 1; + serial_out(up, UART_OMAP_OSC_12M_SEL, 1); + } else + serial_out(up, UART_OMAP_OSC_12M_SEL, 0); + } +#endif + if (up->capabilities & UART_NATSEMI) { /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */ serial_outp(up, UART_LCR, 0xe0); @@ -1742,6 +1754,11 @@ unsigned int size = 8 << up->port.regshift; int ret = 0; +#ifdef CONFIG_ARCH_OMAP + if (is_omap_port(up->port.membase)) + size = 0x16 << up->port.regshift; +#endif + switch (up->port.iotype) { case UPIO_MEM: if (!up->port.mapbase) --- linus/include/linux/serial_reg.h 2004-10-25 10:33:36.000000000 -0700 +++ linux-omap-dev/include/linux/serial_reg.h 2004-11-01 14:52:36.000000000 -0800 @@ -307,5 +307,19 @@ #define SERIAL_RSA_BAUD_BASE (921600) #define SERIAL_RSA_BAUD_BASE_LO (SERIAL_RSA_BAUD_BASE / 8) +/* + * Extra serial register definitions for the internal UARTs + * in TI OMAP processors. + */ +#define UART_OMAP_MDR1 0x08 /* Mode definition register */ +#define UART_OMAP_MDR2 0x09 /* Mode definition register 2 */ +#define UART_OMAP_SCR 0x10 /* Supplementary control register */ +#define UART_OMAP_SSR 0x11 /* Supplementary status register */ +#define UART_OMAP_EBLR 0x12 /* BOF length register */ +#define UART_OMAP_OSC_12M_SEL 0x13 /* OMAP1510 12MHz osc select */ +#define UART_OMAP_MVER 0x14 /* Module version register */ +#define UART_OMAP_SYSC 0x15 /* System configuration register */ +#define UART_OMAP_SYSS 0x16 /* System status register */ + #endif /* _LINUX_SERIAL_REG_H */ | |