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SubjectRe: Concurrent access to /dev/urandom
>Even timer interrupts are incredibly unpredictable.  Instructions can
>variable times to complete, and all instructions plus some indeterminate
>cache operations and queue flushing must occur before the CPU can
>even begin to service an interrupt.

Well, don't timer interrupts happen every 1/1000 s (unless, of course, cli() is
in effect)?

>Also of note, there are small
>sections with interrupts disabled scattered all over the kernel and
>in addition to varying memory latencies, etc. (NOTE: I am not an arch

In case you mean the RDTSC, it is of course better than the I8042, for

Jan Engelhardt
Gesellschaft für Wissenschaftliche Datenverarbeitung
Am Fassberg, 37077 Göttingen,
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