Messages in this thread | | | Date | Sat, 13 Nov 2004 12:46:34 -0700 | From | Grant Grundler <> | Subject | Re: [PATCH] pci-mmconfig fix for 2.6.9 |
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On Sat, Nov 13, 2004 at 08:22:50AM -0800, Michael Chan wrote: > > If I got the discussion so far correctly then the PCI-SGI spec does not > > guarantee that there is no posting, but you know that the chipset > > you are using right now doesn't do it. > > Yes, that's my understanding of the spec. Grant Grundler does not agree > and thinks that non-posting is the only compliant implementation.
That's not what I said. I think we do agree. I'll rephrase. The code currently in arch/i386 and arch/x86_64 support a chipset that is compliant with the part of the spec that requires non-postable config writes.
Other chipsets can implement postable config space. To be compliant with the ECN, the architecture must define a method to guarantee the posted writes have reached the target device. I think the ECN we've been talking about assumes that method will be implemented in firmware somehow and NOT as a direct access method in the OS.
> I wish he was right as it would be the easiest to deal with. > We contacted Intel about the out-of-spec readl when writing to > the PMCSR to change power state as they were the original author > of the mmconfig code. Their solution was to remove the readl after > confirming that mmconfig was non-posted on their chipsets.
That means someone has to introduce a new method to access mmconfig if they implement postable writes.
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