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SubjectRe: Semaphore assembly-code bug

On Fri, 29 Oct 2004, dean gaudet wrote:
> for p4 model 0 through 2 it was faster to avoid lea and shl and generate
> code like:
> add %ebx,%ebx
> add %ebx,%ebx
> add %ebx,%ebx
> add %ebx,%ebx

I think that is true only for the lea's that have a shifted input. The
weakness of the original P4 is its shifter, not lea itself. And for a
simple lea like 4(%esp), it's likely no worse than a regular "add", and
there lea has the advantage that you can put the result in another
register, which can be advantageous in other circumstances.

So lea actually _is_ useful for doing adds, in many cases. Of course, on
older CPU's you'll see the effect of the address generation adder being
one cycle "off" (earlier) the regular ALU execution unit, so lea often
causes AGI stalls. I don't think this is an issue on the P6 or P4 because
of how they actually end up implementing the lea in the regular ALU path.

How the hell did we get to worrying about this in the first place?

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