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    SubjectRe: [PATCH] fix remap of shared read only mappings
    On Thu, 2003-09-04 at 18:56, Jamie Lokier wrote:
    > You have just argued _against_ worrying about cache coherence by
    > aligning mapping addresses.
    > Basically, POSIX says shared mappings aren't guanteed to be coherent
    > until you call msync(). Then you can just do whatever is needed to
    > make different views coherent. That's easier now that we have rmap.

    I think you may misunderstand what I mean by coherence: Our problem is
    the VIVT processor caches. Once one mapper does an msync, that data
    must be visible to all the other mappers, so at that point we have to
    flush the cache lines of all the other mappers. On PA, we only need to
    flush one correctly aligned address to get the VIVT cache to flush all
    the others. However, the kernel page cache usually holds an unaligned
    reference so we need to do the extra aligned flush when this data
    changes. If we didn't do the alignment, we'd need to flush every
    virtual address in the current CPU translation for that page.

    If you mean PROT_SEM requires immediate coherence without an msync, then
    those semantics would be very tricky to achieve on parisc since we'd
    need the kernel virtual address of the page in the page cache correctly
    aligned as well.

    rmap isn't really necessary for this, that's what the
    page->mapping->i_mmap and i_mmap_shared lists are for.


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