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SubjectRe: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this
On Mon, Sep 01, 2003 at 11:12:24AM +0100, Jamie Lokier wrote:
> Russell King wrote:
> > This looks like an old kernel on your NetWinder. Later 2.4 kernels
> > should get this right (by marking the pages uncacheable in user space.)
> How do they know which pages to mark uncacheable? Surely not all
> MAP_SHARED|MAP_FIXED mappings are uncacheable?

By looking at the mappings present in the process. If a process maps the
same file using MAP_SHARED _and_ we fault the same page of data into two
or more mappings, we turn off the cache for those pages.

We actually only turn off the cache and leave the write buffer (aka your
store buffer) turned on for these regions, which should be sufficient for
it to remain coherent between different virtual addresses.

I've been doing some further investigation, and I'm now of the opinion
that "SA110" StrongARM chips have buggy write buffers, because:

- if I turn off the cache, leaving the write buffer on, this program
works on StrongARM-1110 CPUs but not some StrongARM-110 CPUs.
- if I turn off the cache and write buffer on these twice-mapped pages,
StrongARM-110 behaves as expected.

I've tested on several silicon revisions of StrongARM-110's:
- H appears buggy (reports as rev. 2)
- K appears fine (reports as rev. 2)
- S appears buggy (reports as rev. 3)

Unfortunately, the written documentation makes zero mention of the exact
write buffer behaviour. The best that I have to go on for the
StrongARM-110 is a block diagram which indicates that the write buffer
uses physical addresses, and that the D-cache contains the physical
address which the line was fetched from for writeback (via the write

So it seems your test program finds problems which DaveM's aliastest
program fails to detect... Gah. ;(

I guess its time to devise a kernel test and alter our behaviour on ARM

Russell King ( The developer of ARM Linux

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