Messages in this thread | | | Date | Fri, 29 Aug 2003 12:17:38 +0100 | From | Russell King <> | Subject | Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this |
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On Fri, Aug 29, 2003 at 01:08:51PM +0200, Andi Kleen wrote: > Jamie Lokier <jamie@shareable.org> writes: > > data cache is 64k. (The explanation is easy: virtually indexed, > > physically tagged cache moves data among cache lines, possibly via L2). > > On x86 L2 is usually physically tagged. > > Mostly only ARM,MIPS et.al. have virtually tagged L2.
Correction: ARM L1 is mostly VIVT. L2 cache isn't mandated by the architecture, and therefore generally doesn't exist.
-- Russell King (rmk@arm.linux.org.uk) The developer of ARM Linux http://www.arm.linux.org.uk/personal/aboutme.html
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