Messages in this thread | | | Subject | Re: [BUG] slab debug vs. L1 alignement | From | James Bottomley <> | Date | 17 Aug 2003 12:27:41 -0500 |
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Perhaps we should remind ourselves what the alignment rules actually are for kmalloc:
1) No two kmalloc allocations may share cache lines (otherwise data corruption will result). 2) kmalloc should be on a power of two alignment consistent with the widest processor data access requirements.
Now note that 1) is optional (but an efficiency speed up) for a coherent architecture. It is an *absolute requirement* for a non-coherent architecture.
2) is essentially what's causing Ben the problems. His driver appears to be insisting that DMA be a full PCI cache line width. I can see arguments for making this a driver problem.
However, as far as the redzoning issue goes, I think in order to avoid cache line interference, the redzone should be sized to be a cache line width, at least on non-coherent architectures.
In theory, the above should solve everyone's problems.
As far as I/O from user land goes (especially to tape), the users usually can work out the alignment constraints and act accordingly. I'm agnostic as to whether we should fail (with an error indicating alignment problems) or rebuffer causing inefficiency in throughput in the misaligned case.
James
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