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Subject[PATCH] interlace and doublescan modes support for tdfxfb in 2.6
Like the second tdfxfb patch I've posted a while ago - it was posted to
linux-fbdev-devel few days ago, but I haven't got any feedback...

It works on my Voodoo4 4500 and shouldn't cause any problems on other
Voodoos - it's just a port of changes between 2.4.20 and 2.4.21.


----- Forwarded message from Jakub Bogusz <qboosh at pld-linux.org> -----

Date: Sun, 10 Aug 2003 01:24:55 +0200
From: Jakub Bogusz <qboosh at pld-linux.org>
To: linux-fbdev-devel at lists.sourceforge.net
Subject: [PATCH] interlace and doublescan modes support for tdfxfb in 2.6

Hello,

this patch adds interlace and doublescan modes support to tdfxfb in 2.6
(it's a port of changes already incorporated into 2.4.21).

[...]

--
Jakub Bogusz http://cyber.cs.net.pl/~qboosh/
PLD Linux http://www.pld-linux.org/
This patch adds interlace and double-scan mode support to tdfxfb in 2.6.
It's a port of my changes (incorporated into 2.4.21) to Linux 2.6.

-- Jakub Bogusz <qboosh@pld-linux.org>

--- linux-2.6.0-test3/include/video/tdfx.h.orig 2003-07-14 05:32:41.000000000 +0200
+++ linux-2.6.0-test3/include/video/tdfx.h 2003-08-09 21:28:04.000000000 +0200
@@ -114,6 +114,7 @@
#define VGAINIT1_MASK 0x1fffff
#define VIDCFG_VIDPROC_ENABLE BIT(0)
#define VIDCFG_CURS_X11 BIT(1)
+#define VIDCFG_INTERLACE BIT(3)
#define VIDCFG_HALF_MODE BIT(4)
#define VIDCFG_DESK_ENABLE BIT(7)
#define VIDCFG_CLUT_BYPASS BIT(10)
--- linux-2.6.0-test3/drivers/video/tdfxfb.c.orig 2003-08-09 21:26:11.000000000 +0200
+++ linux-2.6.0-test3/drivers/video/tdfxfb.c 2003-08-09 22:52:20.000000000 +0200
@@ -508,8 +508,10 @@
return -EINVAL;
}

- /* fixme: does Voodoo3 support interlace? Banshee doesn't */
- if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
+ /* Banshee doesn't support interlace, but Voodoo4/5 and probably Voodoo3 do. */
+ /* no direct information about device id now? use max_pixclock for this... */
+ if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
+ (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
DPRINTK("interlace not supported\n");
return -EINVAL;
}
@@ -616,10 +618,17 @@
hbs = hd;
hbe = ht;

- vbs = vd = info->var.yres - 1;
- vs = vd + info->var.lower_margin;
- ve = vs + info->var.vsync_len;
- vbe = vt = ve + info->var.upper_margin - 1;
+ if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
+ vbs = vd = (info->var.yres << 1) - 1;
+ vs = vd + (info->var.lower_margin << 1);
+ ve = vs + (info->var.vsync_len << 1);
+ vbe = vt = ve + (info->var.upper_margin << 1) - 1;
+ } else {
+ vbs = vd = info->var.yres - 1;
+ vs = vd + info->var.lower_margin;
+ ve = vs + info->var.vsync_len;
+ vbe = vt = ve + info->var.upper_margin - 1;
+ }

/* this is all pretty standard VGA register stuffing */
reg.misc[0x00] = 0x0f |
@@ -742,8 +751,16 @@
reg.gfxpll = do_calc_pll(..., &fout);
#endif

- reg.screensize = info->var.xres | (info->var.yres << 12);
- reg.vidcfg &= ~VIDCFG_HALF_MODE;
+ if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
+ reg.screensize = info->var.xres | (info->var.yres << 13);
+ reg.vidcfg |= VIDCFG_HALF_MODE;
+ reg.crt[0x09] |= 0x80;
+ } else {
+ reg.screensize = info->var.xres | (info->var.yres << 12);
+ reg.vidcfg &= ~VIDCFG_HALF_MODE;
+ }
+ if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
+ reg.vidcfg |= VIDCFG_INTERLACE;
reg.miscinit0 = tdfx_inl(par, MISCINIT0);

#if defined(__BIG_ENDIAN)
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