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SubjectRe: 2.6.0-test3-mm1: scheduling while atomic (ext3?)
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On Mer, 2003-08-13 at 10:55, Andrew Morton wrote:
> Jurriaan on adsl-gate <thunder7@xs4all.nl> wrote:
> >
> > > Exactly what sort of CPU are you using?
> > > -
> > AMD Athlon XP2400+ on a VIA KT400 chipset, single CPU-system.
>
> OK, thanks. The word is that Athlons will, very occasionally,
> take a fault when prefetching from an unmapped address.

Page zero in the kernel is mapped in 4Mb paging mode (which is what the
Athlon uses). Also your likely(pos) pretty much wiped out the point of
prefetching and punishes other processors because it is in the wrong
place. For that matter we could add a LIST_NULL that pointed somewhere
safe and wasn't NULL per se in 2.7.

Put the likely(pos) in the asm/prefetch for Athlon until someone can
figure out what is going on with some specific Athlons, 2.6 and certain
kernels (notably 4G/4G).

Long term we really do need to start supporting a zero page mapped at
0->64K when not debugging the kernel, then you can let the compiler do
NULL dereferences which is a _huge_ win because you can move stuff
around a lot of natural C conditionals to get better unrolling and
instruction scheduling.

The alternative is to start doing multipointer lists which is messier
and uses more memory (ie each node has next, prev, "several nodes on")

Alan

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