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    SubjectRe: [patch] cache flush bug in mm/filemap.c (all kernels >= 2.5.30(at least))
    Russell King writes:
    > Lothar - can you confirm that your problem vanishes when you turn off
    > write allocation on the caches please? (cachepolicy=writeback)
    >
    No, its still there. But I seem to be unable to turn writealloc ON
    anyway. I get:
    |CPU: XScale-PXA250 [69052904] revision 4 (ARMv5TE)
    |CPU: D undefined 5 cache
    |CPU: I cache: 32768 bytes, associativity 32, 32 byte lines, 32 sets
    |CPU: D cache: 32768 bytes, associativity 32, 32 byte lines, 32 sets
    |Machine: KARO electronics PXA25x module
    |Memory policy: ECC disabled, Data cache write back
    no matter whether I specify 'cachepolicy=writeback', '...writealloc'
    or no cachepolicy at all.
    (This is because ARMv5TE is not recognized as an ARMv5 architecture and
    PMD_SECT_WBWA is turned into PMD_SECT_WB in build_mem_type_table()
    ('arch/arm/mm/mm-armv.c' line 304).
    Another bug?)
    Shouldn't it be:
    @@ -295,12 +295,13 @@
    /*
    * ARMv5 can use ECC memory.
    */
    - if (cpu_arch == CPU_ARCH_ARMv5) {
    + if (cpu_arch == CPU_ARCH_ARMv5 || cpu_arch == CPU_ARCH_ARMv5T ||
    + cpu_arch == CPU_ARCH_ARMv5TE) {
    mem_types[MT_VECTORS].prot_l1 |= ecc_mask;
    mem_types[MT_MEMORY].prot_sect |= ecc_mask;
    } else {
    mem_types[MT_MINICLEAN].prot_sect &= ~PMD_SECT_TEX(1);
    if (cachepolicy == PMD_SECT_WBWA)
    cachepolicy = PMD_SECT_WB;
    ecc_mask = 0;
    }

    Only 'cachepolicy=writethrough' makes the problem disappear.


    Lothar
    -
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