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SubjectRe: [patch] cache flush bug in mm/filemap.c (all kernels >= 2.5.30(at least))
On Fri, May 23, 2003 at 11:29:26AM -0700, Andrew Morton wrote:
> Vague statement of principle: The device driver layer takes care of these
> issues for DMA transfers, and hence should also take care of them for PIO.
> Is this sensible and/or possible?

I'd err on the side of caution about extending this principle. The
device driver layer's issue for DMA transfers seems to cover the device <->
kernel cache consistency, not the device <-> user space or kernel <->
user space cache consistency.

The kernel <-> user space consistency issue seems to be one for the MM
layer to deal with. There are other situations where this view can go
out of sync - for instance, when you have a page of a file mmap'd, and
you use sys_write() to that page of file. This is the issue which
flush_dcache_page() seems to be addressing, and it's the same issue
with PIO from IDE.

So no, I don't think it is a device driver issue at all.

DaveM?

--
Russell King (rmk@arm.linux.org.uk) The developer of ARM Linux
http://www.arm.linux.org.uk/personal/aboutme.html

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