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SubjectRe: [0/4][via-rhine] Improvements

On Sat, 15 Feb 2003, Roger Luethi wrote:
>
> Thanks for raising that issue. It is my understanding that PIO ops are
> synchronous (on IA-32). If that is correct, problems should only occur if
> the driver is built with MMIO support, no?

No, even PIO ops are asynchronous. They are _more_ synchronous than the
MMIO ones (I think the CPU waits until they hit the bus, and most bridges
just pass them through), but the CPU does not wait for them to hit the
device.

So in practice, this _tends_ to mean that a PIO write will usually hit the
device within a microsecond or less of being issued by the CPU, and you
don't need a IO read to force it out. But considering the wide variety of
PCI bridges out there I bet there are some that will post even PIO writes
and might hold on to them for some time, especially if other activity like
DMA keeps the bus busy.

In other words: I suspect the code will work. But it's probably _safer_ to
do the normal "read to synchronize" unless there are major performance
issues (which is clearly not the case in this particular instance, but
might be somewhere else).

Linus

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