Messages in this thread | | | Subject | Re: Page aging broken in 2.6 | From | Benjamin Herrenschmidt <> | Date | Fri, 26 Dec 2003 20:58:27 +1100 |
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On Fri, 2003-12-26 at 20:21, Arjan van de Ven wrote: > > > And we never flush the TLB entry. > > > > > > I don't know if x86 (or other archs really using page tables) will > > > actually set the referenced bit again in the PTE if it's already set > > > in the TLB, if not, then x86 needs a flush too. > > > > x86 needs a flush_tlb_page(), yes. > > it does? Are you 100% sure ? > > Afaik x86 is very very slow in setting the A and D bits (like 2000 to > 3000 cycles) *because* it doesn't need a TLB flush....
How does this work ? If x86 always update those bits even when the TLB copy has them already set, then it will keep writing to the PTEs on every access... which I doubt it does ;) Or does it snoop accesses to the PTE to "catch" somebody clearing the bits ?
Ben.
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