Messages in this thread | | | Date | Tue, 18 Nov 2003 09:28:18 -0500 (EST) | From | Zwane Mwaikambo <> | Subject | Re: FEATURE REQUEST: Specific Processor Optimizations on x86 Architecture |
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On Mon, 27 Oct 2003, Andi Kleen wrote:
> Zwane Mwaikambo <zwane@arm.linux.org.uk> writes: > > > On Mon, 27 Oct 2003, Andi Kleen wrote: > > > > > The wmb() change is not needed, unless you have an oostore CPU > > > (x86 has ordered writes by default). It probably does not hurt > > > neither though (I do it the same way on x86-64), but also doesn't > > > change anything. > > > > The original intent was to fix an SMP P5 system, it oopses otherwise under > > load. > > That doesn't make any sense. P5 doesn't support SFENCE.
I think i misparsed what you were referring to, i thought it was the patch with the barrier in smp_call_function().
My bad.
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