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SubjectRE: [PATCH][2.4] generic cluster APIC support for systems with more than 8 CPUs
Hi Andrew,

> I am seeing if I can get together a test for Netbench with/without
> patch.
> Looking at the patch, I would expect a slight increase in performance.
> I'll
> let you know the results as soon as I have them.
[NK] Thanks for trying it out. The numbers from my post may be useful to


> I do have one question for you: Have you tested netperf using only
> gigabit adapter? If so, have you been able to max out the adapter
> using
> hyperthreading? If not, could you test this? So far I have not been
> to, while I can quite easily with no hyperthreading (in Netbench).
This is
> the case with both irq_balance and irq affinity. having ints
processed by
> one and only one logical CPU at one time really seems to bottleneck
> network
> throughput. I'm sure some of this has to do with sharing those
> among 2 logical CPUs, but I also wonder if int processing is just a
> slower than P3 overall.

[NK] While testing we had 4 100mbps NICs with 4 Way Intel P4 Xeon
1.6GHz. What is your system configuration? Some numbers from your
experiments would be useful in understanding the situation better. Also
what do you mean by no hyper-threading, Is HT disabled in the BIOS, or
the HT awareness is disabled in the code. I need more details of your
setup to test it out.

> I am bringing this up, because I recall James Cleverdon having some
> which
> allows interrupts to be dynamically routed to two CPU destinations, a
> of
> CPUs with consecutive CPU ID's. Interrupts are dynamically routed to
> least loaded CPU, and if both are idle, to the CPU with the lower
> I
> like this idea, because when in HT, if consecutive logical CPU ID's
map to
> one physical core, we get to use "whole" processor, and both
> share the cache. Anyway, just a thought.

[NK] This case will work well if the CPUs are lightly loaded. For
Heavily loaded CPUs to let then perform their on task, it is required to
move the interrupts out of the package.


> -Andrew Theurer
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