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SubjectRe: [PATCH] __cacheline_aligned_in_smp?
On Mon, 13 Jan 2003, David S. Miller wrote:

> From: Rusty Russell <rusty@rustcorp.com.au>
> Date: Tue, 14 Jan 2003 12:10:12 +1100
>
> Hmm, you really want to weakly align it: you don't care if something follows it on
> the cacheline, (ie. don't make it into an array, but it'd be nice if other
> things could share the cacheline) in UP.
>
> No, that is an incorrect statement.
>
> I want the rest of the cacheline to be absent of any write-possible
> data. There are many members in there which are read-only and thus
> will only consume a cacheline which would never need to be written
> back to main memory due to modification.
>
> If you allow other things to seep into that cache line, you totally
> obliterate what I was trying to accomplish.

Am I missing something here? If you have ro and rw data in a cache line:
1r 0w if you don't modify the data
1r 1w if you do
if you have ro and rw in separate cache lines:
2r 0w if you don't modify the data
2r 1w if you do

It would seem that you always have at least one read, and if you modify
the data at least one write, wherein is the saving?

Note: I am not disagreeing with you, I just can't follow how this is a
win in any case.

--
bill davidsen <davidsen@tmr.com>
CTO, TMR Associates, Inc
Doing interesting things with little computers since 1979.

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