Messages in this thread | | | From | Mikael Pettersson <> | Date | Wed, 15 Jan 2003 09:34:28 +0100 | Subject | Re: new CPUID bit |
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James H. Cloos Jr. writes: > Ulrich> Northwood P4's have one more bit in the CPUID processor info > Ulrich> set: bit 31. Intel calls the feature PBE (Pending Break > Ulrich> Enable). > > For the curious, from <http://www.aceshardware.com/forum?read=80030620>: > > Adrian> Bit 31 is PBE (Pending Break Enable) which you can find in the > Adrian> latest P4 instruction manual (document 24547106, page > Adrian> 159-162). To quote:
A better reference for this stuff is (IMHO) AP-485, the "Intel Processor Identification and the CPUID Instruction" application note. It's regularly updated, and in this particular case, its description of CPUID with EAX=1 differs from the IA32 Volume 2 manual (245471xx) in two ways:
- EBX bit 31 is called "SBF", Signal Break on FERR. - ECX is defined to contain additional feature flags. Currently only one is defined: ECX bit 10 is the "Context ID" feature for putting the L1 D-cache in adaptive or shared mode, which matters for hyper-threaded CPUs.
Supporting the new ECX feature flags in the kernel will require some surgery, since the current code assumes x86_capability[0] is Intel, [1] is AMD, [2] is Transmeta, and [3] is for conflicting or synthesized feature flags. We either shift AMD etc down one index and put ECX in [1], or add a new index [4] for ECX, or kludge the few ECX-defined features in [3].
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