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SubjectRE: [PATCH] (0/7) Finish moving NUMA-Q into subarch, cleanup

>Actually, I've also been feeling pain about MAX_IRQ_SOURCES, NR_IRQS,
>and HARDIRQ_BITS in addition to MAX_IO_APICS and MAX_APICS. I'll bet
>some ppl will have trouble with MAX_MP_BUSSES also, though I don't
>have any heavily-populated systems to stress that with.

... and one more from me: isn't it time to let IO-APIC id be 8 bit in the
asm/io_apic.h (make it a union fot both?..)?
Look what I have to do in io_apic.h to get around it and ... "mister, have a
struct IO_APIC_reg_00 {
__u32 __reserved_2 : 24,
ID : 4,
__reserved_1 : 4;
} __attribute__ ((packed));
#ifdef CONFIG_ES7000
struct IO_APIC_reg_00_1 {
__u32 __reserved_2 : 24,
ID : 8;
} __attribute__ ((packed));
#endif /* CONFIG_ES7000 */

and then in io_apic.c:

#ifdef CONFIG_ES7000
struct IO_APIC_reg_00_1 reg_00_1;
unsigned long *reg_00_p;

if (es7000_plat)
reg_00_p = (unsigned long *)&reg_00_1;
reg_00_p = (unsigned long *)&reg_00;
#endif /*CONFIG_ES7000*/
#ifndef CONFIG_ES7000
*(int *)&reg_00 = io_apic_read(apic, 0);
*(int *)reg_00_p = io_apic_read(apic, 0);
#endif /*CONFIG_ES7000*/

>There are also somewhat deeper issues with vector assignments to
>interrupt sources that prevent elevating any of the above to useful
>levels and utilizing them. The assumptions based on the vector assignment
>algorithm appear to be widely distributed enough to discourage me after
>an initial attempt or two to get any kind of useful interrupt routing
>for a number of IRQ sources larger than the number of vectors.

I strongly suggest to take a look in IA64 implementation.
They have 1:1 correspondence between IRQ and vector and don't seem to be
able to run out of vectors or IRQs.

>I pretty much reprogrammed the IDT to push only the vector and then still
>got interrupts on the wrong node(s) despite the physical broadcast RTE's
>plus (node, vector) <-> irq accounting and irq number lookup in do_IRQ().

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