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SubjectRe: Linux 2.4.21-pre3-ac4
On Sun, 2003-01-12 at 20:51, Benjamin Herrenschmidt wrote:
> On Sun, 2003-01-12 at 21:27, Alan Cox wrote:
> > which currently has two problems Ross found
> >
> > 1. The processors or so fast we have to enforce the 400nS delay nowdays
> What about PCI write posting ? How can we enforce the 400ns delay here ?
> I suspect we can't read back from the taskfile registers after writing
> the command. Especially when using DMA, I think I remember Andre telling
> me even tapping alt status might not be safe... So we need to issue
> a read from the same bus path, but not on any taskfile register from
> this channel... hrm... any idea ?

Actually, do we really need that delay as we are waiting for an
interrupt anyway ? my understanding is that this delay is the required
before we start polling for BSY bit (that is the max time the drive may
take to assert BSY after getting the command), but in our case, unless
we have other bugs, we shall have the channel marked busy, so nobody
will tap it, except the actual interrupt coming in. Or will the case of
shared interrupt potentially cause a read of status at the wrong time ?


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