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SubjectRe: 2.4.20pre7, aic7xxx-6.2.8: Panic: HOST_MSG_LOOP with invalid SCB 0
Date
>> This issue has already been resolved as a chipset issue requiring
>> I/O mapped register access to work around. The "old" aic7xxx driver
>> avoids these issues by issuing a register read after every register
>> write. This stops up your PCI bus with wasted cycles even if you have
>> a perfectly working chipset.
>>
>> So, how would you like me to resolve this. We can do the same thing
>> as Adaptec's windows drivers and just always use the slower, less
>> efficient I/O mapped method for accessing registers. This will "fix"
>> the problems people have with broken VIA and Intel chipsets. I can
>> make this a compile and run-time option, but should we default to
>> I/O mapped or memory mapped?
>>
>> Don't you just love broken PC hardware?
>
>Its all fine, then: I thought the problems were caused by some bug in the
>driver itself.
>
>Thanks for explaining me the issue clearly. :)

Hi Justin ! What is the actual breakage here ? Is this just PCI write
posting ? (that is PCI writes staying in bridge write buffer for
some time until you flush the whole path with a read). In this
case those intel & VIA chipsets aren't at fault as this is perfectly
legal per PCI spec and we'll have problem with all other sort of
machines, especially machines with stacked PCI<->PCI bridges like
it's the case for most pmacs.

Or is there a real Intel/VIA bug regarding PCI write buffers ?

I doubt it would affect only Adaptec cards then...

Ben.


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