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SubjectRe: Info: NAPI performance at "low" loads
"David S. Miller" wrote:
>
> From: Andrew Morton <akpm@digeo.com>
> Date: Tue, 17 Sep 2002 14:45:08 -0700
>
> "David S. Miller" wrote:
> > Well, it is due to the same problems manfred saw initially,
> > namely just a crappy or buggy NAPI driver implementation. :-)
>
> It was due to additional inl()'s and outl()'s in the driver fastpath.
>
> How many? Did the implementation cache the register value in a
> software state word or did it read the register each time to write
> the IRQ masking bits back?
>

Looks like it cached it:

- outw(SetIntrEnb | (inw(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD);
vp->intr_enable &= ~StatsFull;
+ outw(vp->intr_enable, ioaddr + EL3_CMD);

> It is issues like this that make me say "crappy or buggy NAPI
> implementation"
>
> Any driver should be able to get the NAPI overhead to max out at
> 2 PIOs per packet.
>
> And if the performance is really concerning, perhaps add an option to
> use MEM space in the 3c59x driver too, IO instructions are constant
> cost regardless of how fast the PCI bus being used is :-)

Yup. But deltas are interesting.
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