[lkml]   [2002]   [Sep]   [17]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
Messages in this thread
SubjectRe: APIC IRQs
On Mon, 16 Sep 2002, James Cleverdon wrote:

> For APICs, when two interrupts are present when interrupts are enabled, the
> one with the highest interrupt vector number will be taken first. Vectors
> are statically assigned to the PCI slots, starting at 0x40 or 0x41. So, the

Vectors start from 0x31. That's what IRQ 0 gets. The interval is 8, so
the following vectors are 0x39, 0x41, and so on.

> last PCI interrupt source in the MPS table will be the highest priority.

Not necessarily -- after reaching the reserved range, i.e. 0xef, the
allocation wraps around to the previous base plus one. So for the second
pass vectors start from 0x32, for the third -- 0x33, etc.

+ Maciej W. Rozycki, Technical University of Gdansk, Poland +
+ e-mail:, PGP key available +

To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to
More majordomo info at
Please read the FAQ at

 \ /
  Last update: 2005-03-22 13:28    [W:0.053 / U:0.048 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site