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SubjectRe: [patch 2.5.31] transparent PCI-to-PCI bridges
On Fri, Aug 30, 2002 at 10:19:58PM +0200, Benjamin Herrenschmidt wrote:
> First, a simple problem: You are showing a possible problem caused
> by a given PCI host & bridge setup. That's not my point. My point
> is that I _do_ have setups with N MMIO regions and want the kernel
> to be able to deal with that.

It's just an example. Give me real numbers and addresses and I'll show
you configuration with _real_ hardware which might work, but won't
with your approach.

> I'm not introducing any limitation to
> the code, I want the code to be generic enough to cope with a setup
> that exist (as the host is configured by my firmware).

You won't allow windows of the PCI bridge to overlap multiple ranges decoded
by the host bridge - it's a serious limitation, I think.

> Also, in your example, if I expose a single memory resource, then I
> lie since the host bridge in this example would not forward addresses
> "between" the 2 ranges, thus the kernel would potentially allocate
> space for unassigned devices in that non-decoded range.

Nope. Arch specific pcibios_align_resource is called on every allocation
and should take care of this - read the code.

> I want my host pci_bus structure to expose what it is really forwarding.
> That's as simple as that. If your host is configured in a more "sane",
> way, then good.

Actually, no. Some old alphas have several (8, IIRC) PCI memory windows
with a 8Mb "hole" in each.

> Regarding your above example, it just don't happen in real life.
> First, we have AGP as a separate PCI host domain on pmac ;) Then,
> the firmware can configures host bridges with large enough regions
> to deal with what is needed by the card.

Pmac firmware is really cool then. ;-) Video cards with 256M memory
regions are quite common and 512M ones already exist.

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