Messages in this thread | | | Subject | Re: No Subject | From | Alan Cox <> | Date | 04 Aug 2002 00:38:00 +0100 |
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On Sat, 2002-08-03 at 23:16, Bartlomiej Zolnierkiewicz wrote: > Just rethough it. What if chipset is in compatibility mode? > Like VIA with base addresses set to 0?
If we found a register that was marked as unassigned with a size then we would map it to a PCI address. That would go for BAR0-3 on any PCI IDE device attached to the south bridge.
What problems does that cause for the VIA stuff ?
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