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SubjectRe: readsw/writesw readsl/writesl
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>it is a bit ugly right now, in asm-m68/ide.h we have to include io.h
>and redefine some of the defs. Even more fun with some net drivers (eg 8390)
>which on m68k can accessed over ISA bus, Zorro bus, or Zorro bus +
>ISA bridge and maybe a few other methods. Byteswaps are the smallest
>problem here, we have also to translate adresses and deal with sparsely
>mapped io regions.
>
>A decent solution should use a per device "busops" struct that would
>define in/out and other access methods for the underlying bus.

This have been proposed several times in the past, and always rejected
for what is I think mostly fantasmatic performances reasons.

Though that would fit nicely in the new driver model ;)

The fact is that an indirect function call has a non-negligible cost
on heavily pipelined CPUs like we have nowadays. But on the other
hand, do we do _that_ much perf critical MMIOs ? Most of the really
perf critical IOs are DMA... We could eventually mix that and provide
direct accessors for PCI in addition to generic per-bus "ops"...

Another possibility (that looks saner to me) would be to define that
the IO macros take all a parameter which represents the bus (or rather
the device pointer in the new driver model). Most archs would just
ignore that macro parameter and so have exactly equivalent code as
we have today, but that let archs that feel they need it to actually
use that to go pick the proper access methods for that device.

In all cases, though, I would keep the distinction between {read,write}*
and {in,out}* as there are PCI drivers that will need to mix them.

But I have few hopes for anything like that to ever be accepted
anyway...

Ben.


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