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SubjectRe: [PATCH] reduce size of bridge regions for yenta.c
dhinds pointed me to a recent thread with another possible workaround:

The ICH-3M bridge is actually a transparent bridge that forwards all
memory IO:

<<<< ich-3M datasheet (29071601.pdf)

MEMBASE Memory Base Register (HUB-PCI D30:F0)
Offset Address: 20 21h Attribute: R/W
Default Value: FFF0h Size: 16 bits
This register defines the base of the hub interface to PCI
non-prefetchable memory range. Since the ICH3 will forward all hub
interface memory accesses to PCI, the ICH3 will only use this
information for determining when not to accept cycles as a target. This
register must be initialized by the configuration software. For the
purpose of address decode, address bits A[19:0] are assumed to be 0.
Thus, the bottom of the defined memory address range will be aligned to
a 1-MB boundary.

Perhaps a pci-quirk should set

bus->resource[1] = bus->parent->resource[1];

for the ICH-3M.

No patch, I don't understand the pci layer good enough to write such a

But IMHO the changes to yenta.c should be applied anyway: allocating 8
MB, without any fallback, without reasonable error output is gross.


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