Messages in this thread |  | | Subject | Re: A question about cache coherence | From | Alan Cox <> | Date | 19 Aug 2002 20:23:03 +0100 |
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On Mon, 2002-08-19 at 19:21, Xuehua Chen wrote: > 1. Do Xeon processors have hardware mechanisms to > maintain cache coherence?
Yes
> 2. Does the SMP kernel handle the cache coherence > problem
The kernel has to manage side issues (TLB shootdown etc)
> 3. What should I do if both of them don't handle cache > coherence.
Debug your code. It is possible you are hitting a kernel bug but its extremely unlikely.
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